This post concerns with the brief summary of my GSoC experience till now.

I made a Run Length Encoder till my mid-term evaluation and Quantizer module is still under process. I have made a divider for quantizer module, I have to make a top level module to get finished with Quantizer module.

I made a PR for my work in the main repo this week. The PR had 40 commits.

The Run Length Encoder takes 8×8 pixels data and outputs the Run Length Encoded data.

Sample input:

red_pixels_1 = [

1, 12, 0, 0, 0, 0, 0, 0,

0, 0, 0, 0, 0, 0, 0, 0,

0, 0, 0, 10, 2, 3, 4, 0,

0, 0, 0, 0, 0, 0, 0, 0,

0, 0, 0, 0, 0, 0, 0, 0,

0, 0, 0, 0, 0, 0, 0, 0,

0, 0, 0, 0, 0, 0, 0, 0,

0, 0, 0, 0, 1, 0, 0, 0

]

red_pixels_2 = [

0, 12, 20, 0, 0, 2, 3, 4,

0, 0, 2, 3, 4, 5, 1, 0,

0, 0, 0, 0, 0, 0, 90, 0,

0, 0, 0, 10, 0, 0, 0, 9,

1, 1, 1, 1, 2, 3, 4, 5,

1, 2, 3, 4, 1, 2, 0, 0,

0, 0, 0, 0, 0, 0, 0, 0,

0, 0, 0, 0, 0, 0, 0, 0

]

green_pixels_1 = [

11, 12, 0, 0, 0, 0, 0, 0,

0, 0, 0, 0, 0, 0, 0, 0,

0, 0, 0, 10, 2, 3, 4, 0,

0, 0, 0, 0, 1, 0, 0, 0,

0, 0, 1, 1, 2, 3, 4, 5,

1, 2, 3, 4, 1, 2, 0, 0,

0, 0, 0, 0, 0, 0, 0, 0,

0, 0, 0, 0, 1, 0, 0, 0

]

green_pixels_2 = [

13, 12, 20, 0, 0, 0, 0, 0,

0, 0, 0, 0, 0, 0, 0, 0,

0, 0, 0, 0, 0, 0, 0, 0,

0, 0, 0, 0, 0, 0, 0, 0,

0, 0, 0, 0, 0, 0, 0, 0,

0, 0, 0, 0, 0, 0, 0, 0,

0, 0, 0, 0, 0, 0, 0, 1,

1, 0, 0, 0, 1, 32, 4, 2

]

blue_pixels_1 = [

11, 12, 0, 0, 0, 0, 0, 0,

0, 0, 0, 0, 0, 0, 0, 0,

0, 0, 0, 0, 0, 0, 0, 0,

0, 0, 0, 0, 0, 0, 0, 0,

0, 0, 0, 1, 2, 3, 4, 5,

1, 2, 3, 4, 1, 2, 0, 0,

0, 0, 0, 0, 0, 0, 0, 0,

0, 0, 0, 0, 0, 0, 0, 1

]

blue_pixels_2 = [

16, 12, 20, 0, 0, 2, 3, 4,

0, 0, 2, 3, 4, 5, 1, 0,

0, 0, 0, 0, 0, 0, 90, 0,

0, 0, 0, 10, 0, 0, 0, 9,

1, 1, 1, 1, 2, 3, 4, 5,

1, 2, 3, 4, 1, 2, 0, 1,

1, 0, 0, 0, 0, 0, 0, 1,

1, 0, 0, 0, 1, 32, 4, 2

]

Sample output:

============================

runlength 0 size 1 amplitude 1

runlength 0 size 4 amplitude 12

runlength 15 size 0 amplitude 0

runlength 2 size 4 amplitude 10

runlength 0 size 2 amplitude 2

runlength 0 size 2 amplitude 3

runlength 0 size 3 amplitude 4

runlength 15 size 0 amplitude 0

runlength 15 size 0 amplitude 0

runlength 7 size 1 amplitude 1

runlength 0 size 0 amplitude 0

runlength 0 size 0 amplitude 0

============================

runlength 0 size 1 amplitude -2

runlength 0 size 4 amplitude 12

runlength 0 size 5 amplitude 20

runlength 2 size 2 amplitude 2

runlength 0 size 2 amplitude 3

runlength 0 size 3 amplitude 4

runlength 2 size 2 amplitude 2

runlength 0 size 2 amplitude 3

runlength 0 size 3 amplitude 4

runlength 0 size 3 amplitude 5

runlength 0 size 1 amplitude 1

runlength 7 size 7 amplitude 90

runlength 4 size 4 amplitude 10

runlength 3 size 4 amplitude 9

runlength 0 size 1 amplitude 1

runlength 0 size 1 amplitude 1

runlength 0 size 1 amplitude 1

runlength 0 size 1 amplitude 1

runlength 0 size 2 amplitude 2

runlength 0 size 2 amplitude 3

runlength 0 size 3 amplitude 4

runlength 0 size 3 amplitude 5

runlength 0 size 1 amplitude 1

runlength 0 size 2 amplitude 2

runlength 0 size 2 amplitude 3

runlength 0 size 3 amplitude 4

runlength 0 size 1 amplitude 1

runlength 0 size 2 amplitude 2

runlength 0 size 0 amplitude 0

runlength 0 size 0 amplitude 0

=============================

runlength 0 size 4 amplitude 11

runlength 0 size 4 amplitude 12

runlength 15 size 0 amplitude 0

runlength 2 size 4 amplitude 10

runlength 0 size 2 amplitude 2

runlength 0 size 2 amplitude 3

runlength 0 size 3 amplitude 4

runlength 5 size 1 amplitude 1

runlength 5 size 1 amplitude 1

runlength 0 size 1 amplitude 1

runlength 0 size 2 amplitude 2

runlength 0 size 2 amplitude 3

runlength 0 size 3 amplitude 4

runlength 0 size 3 amplitude 5

runlength 0 size 1 amplitude 1

runlength 0 size 2 amplitude 2

runlength 0 size 2 amplitude 3

runlength 0 size 3 amplitude 4

runlength 0 size 1 amplitude 1

runlength 0 size 2 amplitude 2

runlength 14 size 1 amplitude 1

runlength 0 size 0 amplitude 0

runlength 0 size 0 amplitude 0

==============================

runlength 0 size 2 amplitude 2

runlength 0 size 4 amplitude 12

runlength 0 size 5 amplitude 20

runlength 15 size 0 amplitude 0

runlength 15 size 0 amplitude 0

runlength 15 size 0 amplitude 0

runlength 7 size 1 amplitude 1

runlength 0 size 1 amplitude 1

runlength 3 size 1 amplitude 1

runlength 0 size 6 amplitude 32

runlength 0 size 3 amplitude 4

runlength 0 size 2 amplitude 2

runlength 0 size 0 amplitude 0

==============================

runlength 0 size 4 amplitude 11

runlength 0 size 4 amplitude 12

runlength 15 size 0 amplitude 0

runlength 15 size 0 amplitude 0

runlength 3 size 1 amplitude 1

runlength 0 size 2 amplitude 2

runlength 0 size 2 amplitude 3

runlength 0 size 3 amplitude 4

runlength 0 size 3 amplitude 5

runlength 0 size 1 amplitude 1

runlength 0 size 2 amplitude 2

runlength 0 size 2 amplitude 3

runlength 0 size 3 amplitude 4

runlength 0 size 1 amplitude 1

runlength 0 size 2 amplitude 2

runlength 15 size 0 amplitude 0

runlength 2 size 1 amplitude 1

runlength 0 size 0 amplitude 0

==============================

runlength 0 size 3 amplitude 5

runlength 0 size 4 amplitude 12

runlength 0 size 5 amplitude 20

runlength 2 size 2 amplitude 2

runlength 0 size 2 amplitude 3

runlength 0 size 3 amplitude 4

runlength 2 size 2 amplitude 2

runlength 0 size 2 amplitude 3

runlength 0 size 3 amplitude 4

runlength 0 size 3 amplitude 5

runlength 0 size 1 amplitude 1

runlength 7 size 7 amplitude 90

runlength 4 size 4 amplitude 10

runlength 3 size 4 amplitude 9

runlength 0 size 1 amplitude 1

runlength 0 size 1 amplitude 1

runlength 0 size 1 amplitude 1

runlength 0 size 1 amplitude 1

runlength 0 size 2 amplitude 2

runlength 0 size 2 amplitude 3

runlength 0 size 3 amplitude 4

runlength 0 size 3 amplitude 5

runlength 0 size 1 amplitude 1

runlength 0 size 2 amplitude 2

runlength 0 size 2 amplitude 3

runlength 0 size 3 amplitude 4

runlength 0 size 1 amplitude 1

runlength 0 size 2 amplitude 2

runlength 1 size 1 amplitude 1

runlength 0 size 1 amplitude 1

runlength 6 size 1 amplitude 1

runlength 0 size 1 amplitude 1

runlength 3 size 1 amplitude 1

runlength 0 size 6 amplitude 32

runlength 0 size 3 amplitude 4

runlength 0 size 2 amplitude 2

runlength 3 size 4 amplitude 9

==============================

The module if it counts more than 15 zero’s, it stalls the inputs.

I tried to git rebase my repo and I messed up things. Now every thing seems fine.

As per my timeline, I have to finish Quantizer and Run Length Encoder by 28th of this month. I hope to finsih them on time.

Control Unit and Documentation : Remaining time.

I came to know today that while indexing Python excludes the upper bound whereas verilog includes the upper bound.

I set a generic feature to RLE module, so that it can take a y number of pixels.

The RLE Core processes the data and stores it in RLE Double Buffer. when Huffman module reads from one buffer, we can write into the second buffer.

This week I set up travis builder for my repo. Things dint work initially well with the Travis builder, because I imported FIFO from the RHEA folder.

As soon, cfelton released a MyHDL 1.0 Version with block decorator of the RHEA files. Travis builder set things well.

RLE core have a negative number issue initially, which I set up finally.

The code coverage for RLE Moudule is 100 percent as per the pytest.

Landscape gives the code around 90 percent health.

Coveralls give around 100 percent coverage for the code.

I added conversion tests for all the modules. I made a dummy wrapper around each module so that I can check that the test converts or not.

I was facing an issue with nested interfaces, I came to know MyHDL have no support to nested interfaces as ports. They assign them as reg or wire but not input or output.

So, I made bit modifications to my interfaces.

Talking about the Quantizer module.

The module have a divider at its heart made of multiplier. We send a number to rom and get its reciprocal stored in rom. We multiply reciprocal with the divisor and hence we get the output.

The module is already made and will be uploaded mostly by tomorrow on github.

I have been following the same architecture as reference design for Quantizer module.

Also, I made a seperate clock, reset modules in common folder so that I can access things easily and also added a reference implementation in common folder.

I will finish the modules as per the checkpoint’s.

Stay tuned for the next update.